DRAM circuits are typically arranged in accessible rows, columns, and associated control, access or timing logic. Furthermore, since such memory circuits are relatively densely designed in silicon active area, and therefore susceptible to manufacturing defects, redundant circuitry is sometimes provided with conventional DRAMs. Such built-in redundancy allows DRAM manufacturers to test for certain circuit defects, such as column shorts arising from wafer fabrication, and thereby enabling limited circuit reconfiguration around known faulty circuit portions.
Prior-art approach to providing column redundancy with memory circuits is shown in FIG. 1. Here, global column redundancy serves multiple memory blocks, wherein redundant column are sub-divided in multiple segments, each corresponding to memory block or group of blocks. As shown, column redundancy is divided in segments A-D, and each redundant segment has its own controller and corresponds to specific memory block. In simplified implementation of such scheme, global column may be a single segment.
Although such approach serves to replace four independent defects, corresponding to each block, significant prior-art shortcomings include:
(1) Non-Scalability. Each redundancy control circuit is hardwired to a block. If number of blocks is variable, separate circuit design has to be implemented for each situation. PA1 (2) Limited Efficiency. Not efficient when number of blocks is less than number of redundancy control circuits. Also, not efficient in fixing global column fails. To fix single global column fail, all redundant segments are needed. PA1 (3) Row-Address Decoding. Row address is needed to decode column redundancy, thereby resulting in column path delay, particularly with multiple bank memories.